From 05462364c98572485a1d56c4d84921259b33dce2 Mon Sep 17 00:00:00 2001 From: Alex Coplan Date: Mon, 7 Sep 2020 15:23:44 +0100 Subject: [PATCH] aarch64: Remove redundant mult patterns Following on from the previous commit to fix up the syntax for add/sub/adds/subs and friends with a sign/zero-extended operand, this patch removes the "mult" variants of these patterns which are all redundant. This patch removes the following patterns from the AArch64 backend: *adds_mul_imm_ *subs_mul_imm_ *adds__multp2 *subs__multp2 *add_mul_imm_ *add__mult_ *add__mult_si_uxtw *add__multp2 *add_si_multp2_uxtw *add_uxt_multp2 *add_uxtsi_multp2_uxtw *sub_mul_imm_ *sub_mul_imm_si_uxtw *sub__multp2 *sub_si_multp2_uxtw *sub_uxt_multp2 *sub_uxtsi_multp2_uxtw *neg_mul_imm_2 *neg_mul_imm_si2_uxtw Together with the following predicates which were used only by these patterns: aarch64_pwr_imm3 aarch64_pwr_2_si aarch64_pwr_2_di These patterns are all redundant since multiplications by powers of two should be represented as shfits outside a (mem). --- gcc/ChangeLog: * config/aarch64/aarch64.md (*adds_mul_imm_): Delete. (*subs_mul_imm_): Delete. (*adds__multp2): Delete. (*subs__multp2): Delete. (*add_mul_imm_): Delete. (*add__mult_): Delete. (*add__mult_si_uxtw): Delete. (*add__multp2): Delete. (*add_si_multp2_uxtw): Delete. (*add_uxt_multp2): Delete. (*add_uxtsi_multp2_uxtw): Delete. (*sub_mul_imm_): Delete. (*sub_mul_imm_si_uxtw): Delete. (*sub__multp2): Delete. (*sub_si_multp2_uxtw): Delete. (*sub_uxt_multp2): Delete. (*sub_uxtsi_multp2_uxtw): Delete. (*neg_mul_imm_2): Delete. (*neg_mul_imm_si2_uxtw): Delete. * config/aarch64/predicates.md (aarch64_pwr_imm3): Delete. (aarch64_pwr_2_si): Delete. (aarch64_pwr_2_di): Delete. (cherry picked from commit 2f8ae301f6a125f50b0a758047fcddae7b68daa8) Signed-off-by: Kirill A. Korinsky --- gcc/config/aarch64/aarch64.md | 271 ------------------------------- gcc/config/aarch64/predicates.md | 15 -- 2 files changed, 286 deletions(-) diff --git gcc/config/aarch64/aarch64.md gcc/config/aarch64/aarch64.md index 96e72bc6c06..95e24541f07 100644 --- gcc/config/aarch64/aarch64.md +++ gcc/config/aarch64/aarch64.md @@ -2356,38 +2356,6 @@ (define_insn "*subs_shift_imm_" [(set_attr "type" "alus_shift_imm")] ) -(define_insn "*adds_mul_imm_" - [(set (reg:CC_NZ CC_REGNUM) - (compare:CC_NZ - (plus:GPI (mult:GPI - (match_operand:GPI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_pwr_2_" "n")) - (match_operand:GPI 3 "register_operand" "r")) - (const_int 0))) - (set (match_operand:GPI 0 "register_operand" "=r") - (plus:GPI (mult:GPI (match_dup 1) (match_dup 2)) - (match_dup 3)))] - "" - "adds\\t%0, %3, %1, lsl %p2" - [(set_attr "type" "alus_shift_imm")] -) - -(define_insn "*subs_mul_imm_" - [(set (reg:CC_NZ CC_REGNUM) - (compare:CC_NZ - (minus:GPI (match_operand:GPI 1 "register_operand" "r") - (mult:GPI - (match_operand:GPI 2 "register_operand" "r") - (match_operand:QI 3 "aarch64_pwr_2_" "n"))) - (const_int 0))) - (set (match_operand:GPI 0 "register_operand" "=r") - (minus:GPI (match_dup 1) - (mult:GPI (match_dup 2) (match_dup 3))))] - "" - "subs\\t%0, %1, %2, lsl %p3" - [(set_attr "type" "alus_shift_imm")] -) - (define_insn "*adds__" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ @@ -2452,46 +2420,6 @@ (define_insn "*subs__shift_" [(set_attr "type" "alus_ext")] ) -(define_insn "*adds__multp2" - [(set (reg:CC_NZ CC_REGNUM) - (compare:CC_NZ - (plus:GPI (ANY_EXTRACT:GPI - (mult:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n") - (const_int 0)) - (match_operand:GPI 4 "register_operand" "rk")) - (const_int 0))) - (set (match_operand:GPI 0 "register_operand" "=r") - (plus:GPI (ANY_EXTRACT:GPI (mult:GPI (match_dup 1) (match_dup 2)) - (match_dup 3) - (const_int 0)) - (match_dup 4)))] - "aarch64_is_extend_from_extract (mode, operands[2], operands[3])" - "adds\\t%0, %4, %1, xt%e3 %p2" - [(set_attr "type" "alus_ext")] -) - -(define_insn "*subs__multp2" - [(set (reg:CC_NZ CC_REGNUM) - (compare:CC_NZ - (minus:GPI (match_operand:GPI 4 "register_operand" "rk") - (ANY_EXTRACT:GPI - (mult:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n") - (const_int 0))) - (const_int 0))) - (set (match_operand:GPI 0 "register_operand" "=r") - (minus:GPI (match_dup 4) (ANY_EXTRACT:GPI - (mult:GPI (match_dup 1) (match_dup 2)) - (match_dup 3) - (const_int 0))))] - "aarch64_is_extend_from_extract (mode, operands[2], operands[3])" - "subs\\t%0, %4, %1, xt%e3 %p2" - [(set_attr "type" "alus_ext")] -) - (define_insn "*add3nr_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ @@ -2549,16 +2477,6 @@ (define_insn "*add__si_uxtw" [(set_attr "type" "alu_shift_imm")] ) -(define_insn "*add_mul_imm_" - [(set (match_operand:GPI 0 "register_operand" "=r") - (plus:GPI (mult:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_pwr_2_" "n")) - (match_operand:GPI 3 "register_operand" "r")))] - "" - "add\\t%0, %3, %1, lsl %p2" - [(set_attr "type" "alu_shift_imm")] -) - (define_insn "*add__" [(set (match_operand:GPI 0 "register_operand" "=rk") (plus:GPI (ANY_EXTEND:GPI (match_operand:ALLX 1 "register_operand" "r")) @@ -2603,57 +2521,6 @@ (define_insn "*add__shft_si_uxtw" [(set_attr "type" "alu_ext")] ) -(define_insn "*add__mult_" - [(set (match_operand:GPI 0 "register_operand" "=rk") - (plus:GPI (mult:GPI (ANY_EXTEND:GPI - (match_operand:ALLX 1 "register_operand" "r")) - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand:GPI 3 "register_operand" "r")))] - "" - "add\\t%0, %3, %1, xt %p2" - [(set_attr "type" "alu_ext")] -) - -;; zero_extend version of above -(define_insn "*add__mult_si_uxtw" - [(set (match_operand:DI 0 "register_operand" "=rk") - (zero_extend:DI (plus:SI (mult:SI (ANY_EXTEND:SI - (match_operand:SHORT 1 "register_operand" "r")) - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand:SI 3 "register_operand" "r"))))] - "" - "add\\t%w0, %w3, %w1, xt %p2" - [(set_attr "type" "alu_ext")] -) - -(define_insn "*add__multp2" - [(set (match_operand:GPI 0 "register_operand" "=rk") - (plus:GPI (ANY_EXTRACT:GPI - (mult:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n") - (const_int 0)) - (match_operand:GPI 4 "register_operand" "r")))] - "aarch64_is_extend_from_extract (mode, operands[2], operands[3])" - "add\\t%0, %4, %1, xt%e3 %p2" - [(set_attr "type" "alu_ext")] -) - -;; zero_extend version of above -(define_insn "*add_si_multp2_uxtw" - [(set (match_operand:DI 0 "register_operand" "=rk") - (zero_extend:DI - (plus:SI (ANY_EXTRACT:SI - (mult:SI (match_operand:SI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n") - (const_int 0)) - (match_operand:SI 4 "register_operand" "r"))))] - "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])" - "add\\t%w0, %w4, %w1, xt%e3 %p2" - [(set_attr "type" "alu_ext")] -) - (define_expand "add3_carryin" [(set (match_operand:GPI 0 "register_operand") (plus:GPI @@ -2855,38 +2722,6 @@ (define_insn "*add_uxtsi_shift2_uxtw" [(set_attr "type" "alu_ext")] ) -(define_insn "*add_uxt_multp2" - [(set (match_operand:GPI 0 "register_operand" "=rk") - (plus:GPI (and:GPI - (mult:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n")) - (match_operand:GPI 4 "register_operand" "r")))] - "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3])) != 0" - "* - operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), - INTVAL (operands[3]))); - return \"add\t%0, %4, %1, uxt%e3 %p2\";" - [(set_attr "type" "alu_ext")] -) - -;; zero_extend version of above -(define_insn "*add_uxtsi_multp2_uxtw" - [(set (match_operand:DI 0 "register_operand" "=rk") - (zero_extend:DI - (plus:SI (and:SI - (mult:SI (match_operand:SI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n")) - (match_operand:SI 4 "register_operand" "r"))))] - "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3])) != 0" - "* - operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), - INTVAL (operands[3]))); - return \"add\t%w0, %w4, %w1, uxt%e3 %p2\";" - [(set_attr "type" "alu_ext")] -) - (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=rk") (minus:SI (match_operand:SI 1 "register_operand" "rk") @@ -3290,30 +3125,6 @@ (define_insn "*sub__si_uxtw" [(set_attr "type" "alu_shift_imm")] ) -(define_insn "*sub_mul_imm_" - [(set (match_operand:GPI 0 "register_operand" "=r") - (minus:GPI (match_operand:GPI 3 "register_operand" "r") - (mult:GPI - (match_operand:GPI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_pwr_2_" "n"))))] - "" - "sub\\t%0, %3, %1, lsl %p2" - [(set_attr "type" "alu_shift_imm")] -) - -;; zero_extend version of above -(define_insn "*sub_mul_imm_si_uxtw" - [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI - (minus:SI (match_operand:SI 3 "register_operand" "r") - (mult:SI - (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_pwr_2_si" "n")))))] - "" - "sub\\t%w0, %w3, %w1, lsl %p2" - [(set_attr "type" "alu_shift_imm")] -) - (define_insn "*sub__" [(set (match_operand:GPI 0 "register_operand" "=rk") (minus:GPI (match_operand:GPI 1 "register_operand" "rk") @@ -3360,34 +3171,6 @@ (define_insn "*sub__shft_si_uxtw" [(set_attr "type" "alu_ext")] ) -(define_insn "*sub__multp2" - [(set (match_operand:GPI 0 "register_operand" "=rk") - (minus:GPI (match_operand:GPI 4 "register_operand" "rk") - (ANY_EXTRACT:GPI - (mult:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n") - (const_int 0))))] - "aarch64_is_extend_from_extract (mode, operands[2], operands[3])" - "sub\\t%0, %4, %1, xt%e3 %p2" - [(set_attr "type" "alu_ext")] -) - -;; zero_extend version of above -(define_insn "*sub_si_multp2_uxtw" - [(set (match_operand:DI 0 "register_operand" "=rk") - (zero_extend:DI - (minus:SI (match_operand:SI 4 "register_operand" "rk") - (ANY_EXTRACT:SI - (mult:SI (match_operand:SI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n") - (const_int 0)))))] - "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])" - "sub\\t%w0, %w4, %w1, xt%e3 %p2" - [(set_attr "type" "alu_ext")] -) - ;; The hardware description is op1 + ~op2 + C. ;; = op1 + (-op2 + 1) + (1 - !C) ;; = op1 - op2 - 1 + 1 - !C @@ -3643,38 +3426,6 @@ (define_insn "*sub_uxtsi_shift2_uxtw" [(set_attr "type" "alu_ext")] ) -(define_insn "*sub_uxt_multp2" - [(set (match_operand:GPI 0 "register_operand" "=rk") - (minus:GPI (match_operand:GPI 4 "register_operand" "rk") - (and:GPI - (mult:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n"))))] - "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),INTVAL (operands[3])) != 0" - "* - operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), - INTVAL (operands[3]))); - return \"sub\t%0, %4, %1, uxt%e3 %p2\";" - [(set_attr "type" "alu_ext")] -) - -;; zero_extend version of above -(define_insn "*sub_uxtsi_multp2_uxtw" - [(set (match_operand:DI 0 "register_operand" "=rk") - (zero_extend:DI - (minus:SI (match_operand:SI 4 "register_operand" "rk") - (and:SI - (mult:SI (match_operand:SI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n")))))] - "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),INTVAL (operands[3])) != 0" - "* - operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), - INTVAL (operands[3]))); - return \"sub\t%w0, %w4, %w1, uxt%e3 %p2\";" - [(set_attr "type" "alu_ext")] -) - (define_expand "abs2" [(match_operand:GPI 0 "register_operand") (match_operand:GPI 1 "register_operand")] @@ -3787,28 +3538,6 @@ (define_insn "*neg__si2_uxtw" [(set_attr "type" "alu_shift_imm")] ) -(define_insn "*neg_mul_imm_2" - [(set (match_operand:GPI 0 "register_operand" "=r") - (neg:GPI (mult:GPI - (match_operand:GPI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_pwr_2_" "n"))))] - "" - "neg\\t%0, %1, lsl %p2" - [(set_attr "type" "alu_shift_imm")] -) - -;; zero_extend version of above -(define_insn "*neg_mul_imm_si2_uxtw" - [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI - (neg:SI (mult:SI - (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_pwr_2_si" "n")))))] - "" - "neg\\t%w0, %w1, lsl %p2" - [(set_attr "type" "alu_shift_imm")] -) - (define_insn "mul3" [(set (match_operand:GPI 0 "register_operand" "=r") (mult:GPI (match_operand:GPI 1 "register_operand" "r") diff --git gcc/config/aarch64/predicates.md gcc/config/aarch64/predicates.md index 1754b1eff9f..91b51483f33 100644 --- gcc/config/aarch64/predicates.md +++ gcc/config/aarch64/predicates.md @@ -235,21 +235,6 @@ (define_predicate "aarch64_imm24" (and (match_code "const_int") (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)"))) -(define_predicate "aarch64_pwr_imm3" - (and (match_code "const_int") - (match_test "INTVAL (op) != 0 - && (unsigned) exact_log2 (INTVAL (op)) <= 4"))) - -(define_predicate "aarch64_pwr_2_si" - (and (match_code "const_int") - (match_test "INTVAL (op) != 0 - && (unsigned) exact_log2 (INTVAL (op)) < 32"))) - -(define_predicate "aarch64_pwr_2_di" - (and (match_code "const_int") - (match_test "INTVAL (op) != 0 - && (unsigned) exact_log2 (INTVAL (op)) < 64"))) - (define_predicate "aarch64_mem_pair_offset" (and (match_code "const_int") (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))"))) -- 2.42.1