=H9(9\Terasic SoCkit#!altr,socfpga-cyclone5altr,socfpgachosen,console=ttyS0,115200aliases5/soc/ethernet@ff702000?/soc/ethernet@ff702000I/soc/serial0@ffc02000Q/soc/serial1@ffc03000Y/soc/timer0@ffc08000`/soc/timer1@ffc09000g/soc/timer2@ffd00000n/soc/timer3@ffd01000memoryumemory@cpusaltr,socfpga-smpcpu@0!arm,cortex-a9ucpucpu@1!arm,cortex-a9ucpuintc@fffed000!arm,cortex-a9-gicsoc !simple-bususocamba !arm,amba-buspdma@ffe01000!arm,pl330arm,primecell`hijklmno " )apb_pclk$$can@ffc00000 !bosch,d_can0" 5disabledcan@ffc01000 !bosch,d_can0" 5disabledclkmgr@ffd04000 !altr,clk-mgr@clocksosc1< !fixed-clockI}x@osc2< !fixed-clockf2s_periph_ref_clk< !fixed-clock  f2s_sdram_ref_clk< !fixed-clock  main_pll<!altr,socfpga-pll-clock"@mpuclk<!altr,socfpga-perip-clk" Y H  mainclk<!altr,socfpga-perip-clk" Y Ldbg_base_clk<!altr,socfpga-perip-clk" Y Pmain_qspi_clk<!altr,socfpga-perip-clk"Tmain_nand_sdmmc_clk<!altr,socfpga-perip-clk"Xcfg_h2f_usr0_clk<!altr,socfpga-perip-clk"\periph_pll<!altr,socfpga-pll-clock "   emac0_clk<!altr,socfpga-perip-clk" emac1_clk<!altr,socfpga-perip-clk" per_qsi_clk<!altr,socfpga-perip-clk" per_nand_mmc_clk<!altr,socfpga-perip-clk" per_base_clk<!altr,socfpga-perip-clk" h2f_usr1_clk<!altr,socfpga-perip-clk" sdram_pll<!altr,socfpga-pll-clock "   ddr_dqs_clk<!altr,socfpga-perip-clk" ddr_2x_dqs_clk<!altr,socfpga-perip-clk" ddr_dq_clk<!altr,socfpga-perip-clk" h2f_usr2_clk<!altr,socfpga-perip-clk" mpu_periph_clk<!altr,socfpga-perip-clk" a##mpu_l2_ram_clk<!altr,socfpga-perip-clk" al4_main_clk<!altr,socfpga-gate-clk"o`l3_main_clk<!altr,socfpga-perip-clk"al3_mp_clk<!altr,socfpga-gate-clk" Ydo`l3_sp_clk<!altr,socfpga-gate-clk" Ydl4_mp_clk<!altr,socfpga-gate-clk" Ydo`l4_sp_clk<!altr,socfpga-gate-clk" Ydo`dbg_at_clk<!altr,socfpga-gate-clk" Yho`dbg_clk<!altr,socfpga-gate-clk" Yho`dbg_trace_clk<!altr,socfpga-gate-clk" Ylo`dbg_timer_clk<!altr,socfpga-gate-clk"o`cfg_clk<!altr,socfpga-gate-clk"o`h2f_user0_clk<!altr,socfpga-gate-clk"o` emac_0_clk<!altr,socfpga-gate-clk"oemac_1_clk<!altr,socfpga-gate-clk"ousb_mp_clk<!altr,socfpga-gate-clk"o Y%%spi_m_clk<!altr,socfpga-gate-clk"o Y""can0_clk<!altr,socfpga-gate-clk"o Ycan1_clk<!altr,socfpga-gate-clk"o Y gpio_db_clk<!altr,socfpga-gate-clk"o Yh2f_user1_clk<!altr,socfpga-gate-clk"osdmmc_clk<!altr,socfpga-gate-clk " oxsdmmc_clk_divided<!altr,socfpga-gate-clk"oa  nand_x_clk<!altr,socfpga-gate-clk " o nand_clk<!altr,socfpga-gate-clk " o aqspi_clk<!altr,socfpga-gate-clk " o ethernet@ff7000000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac `p  smacirq" )stmmaceth  stmmaceth  5disabledethernet@ff7020000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac `p  xmacirq" )stmmaceth! stmmaceth 5okayrgmii )6CP]j (vi2c@ffc04000!snps,designware-i2c@"  5disabledi2c@ffc05000!snps,designware-i2cP" 5okayaccelerometer@53 !adi,adxl345Si2c@ffc06000!snps,designware-i2c`"  5disabledi2c@ffc07000!snps,designware-i2cp"  5disabledgpio@ff708000!snps,dw-apb-gpiop" 5disabledgpio-controller@0!snps,dw-apb-gpio-port gpio@ff709000!snps,dw-apb-gpiop" 5disabledgpio-controller@0!snps,dw-apb-gpio-port gpio@ff70a000!snps,dw-apb-gpiop"5okaygpio-controller@0!snps,dw-apb-gpio-port sdr@ffc25000!sysconPsdramedac!altr,sdram-edac 'l2-cache@fffef000!arm,pl310-cache &  dwmmc0@ff704000!altr,socfpga-dw-mshcp@ " )biuciu"4E!Q!sram@ffff0000 !mmio-sramspi@fff00000!snps,dw-apb-ssi ^"" 5disabledsnoop-control-unit@fffec000!arm,cortex-a9-scuspi@fff01000!snps,dw-apb-ssi ^"" 5disabledtimer@fffec600!arm,cortex-a9-twd-timer  "#timer0@ffc08000!snps,dw-apb-timer ")timertimer1@ffc09000!snps,dw-apb-timer ")timertimer2@ffd00000!snps,dw-apb-timer ")timertimer3@ffd01000!snps,dw-apb-timer ")timerserial0@ffc02000!snps,dw-apb-uart  eo"|$$txrxserial1@ffc03000!snps,dw-apb-uart0 eo"|$$txrxrstmgr@ffd05000 !altr,rst-mgrPusbphy@0!usb-nop-xceiv5okay&&usb@ffb00000 !snps,dwc2 }"%)otg& usb2-phy 5disabledusb@ffb40000 !snps,dwc2 "%)otg& usb2-phy5okaywatchdog@ffd02000 !snps,dw-wdt  "5okaywatchdog@ffd03000 !snps,dw-wdt0 " 5disabledsysmgr@ffd08000!altr,sys-mgrsysconЀ@Ѐvcc3p3-regulator!regulator-fixedVCC3P32Z2Z!! #address-cells#size-cellsmodelcompatiblebootargsethernet0ethernet1serial0serial1timer0timer1timer2timer3device_typeregenable-methodnext-level-cache#interrupt-cellsinterrupt-controllerlinux,phandleinterrupt-parentrangesinterrupts#dma-cells#dma-channels#dma-requestsclocksclock-namesstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phasealtr,sysmgr-sysconinterrupt-namesmac-addressresetsreset-namessnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthphy-modephy-addrrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxen-skew-pstxc-skew-psrxdv-skew-psrxc-skew-psgpio-controller#gpio-cellssnps,nr-gpiosaltr,sdr-sysconcache-unifiedcache-levelarm,tag-latencyarm,data-latencynum-slotsbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeedvmmc-supplyvqmmc-supplynum-csreg-shiftreg-io-widthdmasdma-names#reset-cells#phy-cellsphysphy-namescpu1-start-addrregulator-nameregulator-min-microvoltregulator-max-microvolt