8(Tti,omap3-evmti,omap3&7TI OMAP35XX EVM (TMDSEVM3530)chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000 d/displaymemorymmemoryycpuscpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmuarm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocpti,omap3-l3-smxsimple-busyh l3_mainl4@48000000ti,omap3-l4-coresimple-bus Hscm@2000ti,omap3-scmsimple-busy  pinmux@30 ti,omap3-padconfpinctrl-singley08pinmux_twl4030_pins8ALRscm_conf@270sysconyp0LRclocksmcbsp5_mux_fckZti,composite-mux-clock}gyhLRmcbsp5_fckZti,composite-clock}mcbsp1_mux_fckZti,composite-mux-clock}gyL R mcbsp1_fckZti,composite-clock} mcbsp2_mux_fckZti,composite-mux-clock} gyL R mcbsp2_fckZti,composite-clock} mcbsp3_mux_fckZti,composite-mux-clock} yhLRmcbsp3_fckZti,composite-clock} mcbsp4_mux_fckZti,composite-mux-clock} gyhLRmcbsp4_fckZti,composite-clock}clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \pinmux_twl4030_vpins 8LRaes@480c5000 ti,omap3-aesaesyH PPtABytxrxprm@48306000 ti,omap3-prmyH0`@ clocksvirt_16_8m_ckZ fixed-clockYLRosc_sys_ckZ ti,mux-clock}y @LRsys_ckZti,divider-clock}gypLRsys_clkout1Zti,gate-clock}y pgdpll3_x2_ckZfixed-factor-clock}dpll3_m2x2_ckZfixed-factor-clock}LRdpll4_x2_ckZfixed-factor-clock}corex2_fckZfixed-factor-clock}LRwkup_l4_ickZfixed-factor-clock}LMRMcorex2_d3_fckZfixed-factor-clock}LRcorex2_d5_fckZfixed-factor-clock}LRclockdomainscm@48004000 ti,omap3-cmyH@@clocksdummy_apb_pclkZ fixed-clockomap_32k_fckZ fixed-clockL?R?virt_12m_ckZ fixed-clockLRvirt_13m_ckZ fixed-clock]@LRvirt_19200000_ckZ fixed-clock$LRvirt_26000000_ckZ fixed-clockLRvirt_38_4m_ckZ fixed-clockILRdpll4_ckZti,omap3-dpll-per-clock}y D 0LRdpll4_m2_ckZti,divider-clock}?y HLRdpll4_m2x2_mul_ckZfixed-factor-clock}L R dpll4_m2x2_ckZti,gate-clock} gy L!R!omap_96m_alwon_fckZfixed-factor-clock}!L(R(dpll3_ckZti,omap3-dpll-core-clock}y @ 0LRdpll3_m3_ckZti,divider-clock}gy@L"R"dpll3_m3x2_mul_ckZfixed-factor-clock}"L#R#dpll3_m3x2_ckZti,gate-clock}#g y L$R$emu_core_alwon_ckZfixed-factor-clock}$LaRasys_altclkZ fixed-clockL-R-mcbsp_clksZ fixed-clockLRdpll3_m2_ckZti,divider-clock}gy @LRcore_ckZfixed-factor-clock}L%R%dpll1_fckZti,divider-clock}%gy @L&R&dpll1_ckZti,omap3-dpll-clock}&y  $ @ 4LRdpll1_x2_ckZfixed-factor-clock}L'R'dpll1_x2m2_ckZti,divider-clock}'y DL;R;cm_96m_fckZfixed-factor-clock}(L)R)omap_96m_fckZ ti,mux-clock})gy @LDRDdpll4_m3_ckZti,divider-clock}g y@L*R*dpll4_m3x2_mul_ckZfixed-factor-clock}*L+R+dpll4_m3x2_ckZti,gate-clock}+gy L,R,omap_54m_fckZ ti,mux-clock},-gy @L7R7cm_96m_d2_fckZfixed-factor-clock})L.R.omap_48m_fckZ ti,mux-clock}.-gy @L/R/omap_12m_fckZfixed-factor-clock}/LFRFdpll4_m4_ckZti,divider-clock} y@L0R0dpll4_m4x2_mul_ckZti,fixed-factor-clock}0L1R1dpll4_m4x2_ckZti,gate-clock}1gy LRdpll4_m5_ckZti,divider-clock}?y@L2R2dpll4_m5x2_mul_ckZti,fixed-factor-clock}2L3R3dpll4_m5x2_ckZti,gate-clock}3gy LiRidpll4_m6_ckZti,divider-clock}g?y@L4R4dpll4_m6x2_mul_ckZfixed-factor-clock}4L5R5dpll4_m6x2_ckZti,gate-clock}5gy L6R6emu_per_alwon_ckZfixed-factor-clock}6LbRbclkout2_src_gate_ckZ ti,composite-no-wait-gate-clock}%gy pL8R8clkout2_src_mux_ckZti,composite-mux-clock}%)7y pL9R9clkout2_src_ckZti,composite-clock}89L:R:sys_clkout2Zti,divider-clock}:g@y pmpu_ckZfixed-factor-clock};L<R<arm_fckZti,divider-clock}<y $emu_mpu_alwon_ckZfixed-factor-clock}<LcRcl3_ickZti,divider-clock}%y @L=R=l4_ickZti,divider-clock}=gy @L>R>rm_ickZti,divider-clock}>gy @gpt10_gate_fckZti,composite-gate-clock}g y L@R@gpt10_mux_fckZti,composite-mux-clock}?gy @LARAgpt10_fckZti,composite-clock}@Agpt11_gate_fckZti,composite-gate-clock}g y LBRBgpt11_mux_fckZti,composite-mux-clock}?gy @LCRCgpt11_fckZti,composite-clock}BCcore_96m_fckZfixed-factor-clock}DLRmmchs2_fckZti,wait-gate-clock}y gLRmmchs1_fckZti,wait-gate-clock}y gLRi2c3_fckZti,wait-gate-clock}y gLRi2c2_fckZti,wait-gate-clock}y gLRi2c1_fckZti,wait-gate-clock}y gLRmcbsp5_gate_fckZti,composite-gate-clock}g y LRmcbsp1_gate_fckZti,composite-gate-clock}g y LRcore_48m_fckZfixed-factor-clock}/LEREmcspi4_fckZti,wait-gate-clock}Ey gLRmcspi3_fckZti,wait-gate-clock}Ey gLRmcspi2_fckZti,wait-gate-clock}Ey gLRmcspi1_fckZti,wait-gate-clock}Ey gLRuart2_fckZti,wait-gate-clock}Ey gLRuart1_fckZti,wait-gate-clock}Ey g LRcore_12m_fckZfixed-factor-clock}FLGRGhdq_fckZti,wait-gate-clock}Gy gLRcore_l3_ickZfixed-factor-clock}=LHRHsdrc_ickZti,wait-gate-clock}Hy gLRgpmc_fckZfixed-factor-clock}Hcore_l4_ickZfixed-factor-clock}>LIRImmchs2_ickZti,omap3-interface-clock}Iy gLRmmchs1_ickZti,omap3-interface-clock}Iy gLRhdq_ickZti,omap3-interface-clock}Iy gLRmcspi4_ickZti,omap3-interface-clock}Iy gLRmcspi3_ickZti,omap3-interface-clock}Iy gLRmcspi2_ickZti,omap3-interface-clock}Iy gLRmcspi1_ickZti,omap3-interface-clock}Iy gLRi2c3_ickZti,omap3-interface-clock}Iy gLRi2c2_ickZti,omap3-interface-clock}Iy gLRi2c1_ickZti,omap3-interface-clock}Iy gLRuart2_ickZti,omap3-interface-clock}Iy gLRuart1_ickZti,omap3-interface-clock}Iy g LRgpt11_ickZti,omap3-interface-clock}Iy g LRgpt10_ickZti,omap3-interface-clock}Iy g LRmcbsp5_ickZti,omap3-interface-clock}Iy g LRmcbsp1_ickZti,omap3-interface-clock}Iy g LRomapctrl_ickZti,omap3-interface-clock}Iy gLRdss_tv_fckZti,gate-clock}7ygLRdss_96m_fckZti,gate-clock}DygLRdss2_alwon_fckZti,gate-clock}ygLRdummy_ckZ fixed-clockgpt1_gate_fckZti,composite-gate-clock}gy LJRJgpt1_mux_fckZti,composite-mux-clock}?y @LKRKgpt1_fckZti,composite-clock}JKaes2_ickZti,omap3-interface-clock}Igy LRwkup_32k_fckZfixed-factor-clock}?LLRLgpio1_dbckZti,gate-clock}Ly gLRsha12_ickZti,omap3-interface-clock}Iy gLRwdt2_fckZti,wait-gate-clock}Ly gLRwdt2_ickZti,omap3-interface-clock}My gLRwdt1_ickZti,omap3-interface-clock}My gLRgpio1_ickZti,omap3-interface-clock}My gLRomap_32ksync_ickZti,omap3-interface-clock}My gLRgpt12_ickZti,omap3-interface-clock}My gLRgpt1_ickZti,omap3-interface-clock}My gLRper_96m_fckZfixed-factor-clock}(L R per_48m_fckZfixed-factor-clock}/LNRNuart3_fckZti,wait-gate-clock}Nyg LRgpt2_gate_fckZti,composite-gate-clock}gyLOROgpt2_mux_fckZti,composite-mux-clock}?y@LPRPgpt2_fckZti,composite-clock}OPgpt3_gate_fckZti,composite-gate-clock}gyLQRQgpt3_mux_fckZti,composite-mux-clock}?gy@LRRRgpt3_fckZti,composite-clock}QRgpt4_gate_fckZti,composite-gate-clock}gyLSRSgpt4_mux_fckZti,composite-mux-clock}?gy@LTRTgpt4_fckZti,composite-clock}STgpt5_gate_fckZti,composite-gate-clock}gyLURUgpt5_mux_fckZti,composite-mux-clock}?gy@LVRVgpt5_fckZti,composite-clock}UVgpt6_gate_fckZti,composite-gate-clock}gyLWRWgpt6_mux_fckZti,composite-mux-clock}?gy@LXRXgpt6_fckZti,composite-clock}WXgpt7_gate_fckZti,composite-gate-clock}gyLYRYgpt7_mux_fckZti,composite-mux-clock}?gy@LZRZgpt7_fckZti,composite-clock}YZgpt8_gate_fckZti,composite-gate-clock}g yL[R[gpt8_mux_fckZti,composite-mux-clock}?gy@L\R\gpt8_fckZti,composite-clock}[\gpt9_gate_fckZti,composite-gate-clock}g yL]R]gpt9_mux_fckZti,composite-mux-clock}?gy@L^R^gpt9_fckZti,composite-clock}]^per_32k_alwon_fckZfixed-factor-clock}?L_R_gpio6_dbckZti,gate-clock}_ygLRgpio5_dbckZti,gate-clock}_ygLRgpio4_dbckZti,gate-clock}_ygLRgpio3_dbckZti,gate-clock}_ygLRgpio2_dbckZti,gate-clock}_yg LRwdt3_fckZti,wait-gate-clock}_yg LRper_l4_ickZfixed-factor-clock}>L`R`gpio6_ickZti,omap3-interface-clock}`ygLRgpio5_ickZti,omap3-interface-clock}`ygLRgpio4_ickZti,omap3-interface-clock}`ygLRgpio3_ickZti,omap3-interface-clock}`ygLRgpio2_ickZti,omap3-interface-clock}`yg LRwdt3_ickZti,omap3-interface-clock}`yg LRuart3_ickZti,omap3-interface-clock}`yg LRuart4_ickZti,omap3-interface-clock}`ygLRgpt9_ickZti,omap3-interface-clock}`yg LRgpt8_ickZti,omap3-interface-clock}`yg LRgpt7_ickZti,omap3-interface-clock}`ygLRgpt6_ickZti,omap3-interface-clock}`ygLRgpt5_ickZti,omap3-interface-clock}`ygLRgpt4_ickZti,omap3-interface-clock}`ygLRgpt3_ickZti,omap3-interface-clock}`ygLRgpt2_ickZti,omap3-interface-clock}`ygLRmcbsp2_ickZti,omap3-interface-clock}`ygLRmcbsp3_ickZti,omap3-interface-clock}`ygLRmcbsp4_ickZti,omap3-interface-clock}`ygLRmcbsp2_gate_fckZti,composite-gate-clock}gyL R mcbsp3_gate_fckZti,composite-gate-clock}gyL R mcbsp4_gate_fckZti,composite-gate-clock}gyLRemu_src_mux_ckZ ti,mux-clock}abcy@LdRdemu_src_ckZti,clkdm-gate-clock}dLeRepclk_fckZti,divider-clock}egy@pclkx2_fckZti,divider-clock}egy@atclk_fckZti,divider-clock}egy@traceclk_src_fckZ ti,mux-clock}abcgy@LfRftraceclk_fckZti,divider-clock}fg y@secure_32k_fckZ fixed-clockLgRggpt12_fckZfixed-factor-clock}gwdt1_fckZfixed-factor-clock}gsecurity_l4_ick2Zfixed-factor-clock}>LhRhaes1_ickZti,omap3-interface-clock}hgy rng_ickZti,omap3-interface-clock}hy gsha11_ickZti,omap3-interface-clock}hy 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@$RLoRossi_ssr_fck_3430es2Zti,composite-clock}noLpRpssi_sst_fck_3430es2Zfixed-factor-clock}pLRhsotgusb_ick_3430es2Z"ti,omap3-hsotgusb-interface-clock}Hy gLRssi_ick_3430es2Zti,omap3-ssi-interface-clock}qy gLRusim_gate_fckZti,composite-gate-clock}Dg y L|R|sys_d2_ckZfixed-factor-clock}LsRsomap_96m_d2_fckZfixed-factor-clock}DLtRtomap_96m_d4_fckZfixed-factor-clock}DLuRuomap_96m_d8_fckZfixed-factor-clock}DLvRvomap_96m_d10_fckZfixed-factor-clock}D LwRwdpll5_m2_d4_ckZfixed-factor-clock}rLxRxdpll5_m2_d8_ckZfixed-factor-clock}rLyRydpll5_m2_d16_ckZfixed-factor-clock}rLzRzdpll5_m2_d20_ckZfixed-factor-clock}rL{R{usim_mux_fckZti,composite-mux-clock(}stuvwxyz{gy @L}R}usim_fckZti,composite-clock}|}usim_ickZti,omap3-interface-clock}My g LRdpll5_ckZti,omap3-dpll-clock}y  $ L 4$6L~R~dpll5_m2_ckZti,divider-clock}~y PLrRrsgx_gate_fckZti,composite-gate-clock}%gy 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#address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinslinux,phandle#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requestssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsti,use_poweroff#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xylinux,wakeuppendown-gpioti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthnon-removablecap-power-off-cardref-clock-frequency#iommu-cellsti,#tlb-entriesstatusreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphysphy-namespowerremote-endpointdata-linesiommusti,phy-typelabelgpioslinux,default-triggerstartup-delay-usenable-active-highvin-supplydefault-onenable-active-lowpower-supplyenable-gpiosreset-gpiosmode-gpios