Ð þí<:H8X(â8+Altera SOCFPGA Arria V SoC Development Kit!!altr,socfpga-arria5altr,socfpgachosen,console=ttyS0,115200aliases5/soc/ethernet@ff702000?/soc/ethernet@ff702000I/soc/serial0@ffc02000Q/soc/serial1@ffc03000Y/soc/timer0@ffc08000`/soc/timer1@ffc09000g/soc/timer2@ffd00000n/soc/timer3@ffd01000memoryumemory@cpuscpu@0!arm,cortex-a9ucpu…cpu@1!arm,cortex-a9ucpu…intc@fffed000!arm,cortex-a9-gic–§ÿþÐÿþÁ¼Âsoc !simple-bususocÊÛamba !arm,amba-busÛpdma@ffe01000!arm,pl330arm,primecellÿà`âhijklmnoíø  apb_pclk¼"Â"can@ffc00000 !bosch,d_canÿÀ0⃄…† 'disabledcan@ffc01000 !bosch,d_canÿÀ0⇈‰Š 'disabledclkmgr@ffd04000 !altr,clk-mgrÿÐ@clocksosc1. !fixed-clock;}x@¼Âosc2. !fixed-clock¼Âf2s_periph_ref_clk. !fixed-clock¼  f2s_sdram_ref_clk. !fixed-clock¼  main_pll.!altr,socfpga-pll-clock@¼Âmpuclk.!altr,socfpga-perip-clk Kà H¼  mainclk.!altr,socfpga-perip-clk Kä L¼Âdbg_base_clk.!altr,socfpga-perip-clk Kè P¼Âmain_qspi_clk.!altr,socfpga-perip-clkT¼Âmain_nand_sdmmc_clk.!altr,socfpga-perip-clkX¼Âcfg_h2f_usr0_clk.!altr,socfpga-perip-clk\¼Âperiph_pll.!altr,socfpga-pll-clock  €¼  emac0_clk.!altr,socfpga-perip-clk ˆ¼Âemac1_clk.!altr,socfpga-perip-clk Œ¼Âper_qsi_clk.!altr,socfpga-perip-clk ¼Âper_nand_mmc_clk.!altr,socfpga-perip-clk ”¼Âper_base_clk.!altr,socfpga-perip-clk ˜¼Âh2f_usr1_clk.!altr,socfpga-perip-clk œ¼Âsdram_pll.!altr,socfpga-pll-clock  À¼  ddr_dqs_clk.!altr,socfpga-perip-clk Èddr_2x_dqs_clk.!altr,socfpga-perip-clk Ìddr_dq_clk.!altr,socfpga-perip-clk Ðh2f_usr2_clk.!altr,socfpga-perip-clk Ômpu_periph_clk.!altr,socfpga-perip-clk S¼!Â!mpu_l2_ram_clk.!altr,socfpga-perip-clk Sl4_main_clk.!altr,socfpga-gate-clka`¼Âl3_main_clk.!altr,socfpga-perip-clkSl3_mp_clk.!altr,socfpga-gate-clk Kda`l3_sp_clk.!altr,socfpga-gate-clk Kdl4_mp_clk.!altr,socfpga-gate-clk Kda`¼Âl4_sp_clk.!altr,socfpga-gate-clk Kda`¼Âdbg_at_clk.!altr,socfpga-gate-clk Kha`dbg_clk.!altr,socfpga-gate-clk Kha`dbg_trace_clk.!altr,socfpga-gate-clk Kla`dbg_timer_clk.!altr,socfpga-gate-clka`cfg_clk.!altr,socfpga-gate-clka`h2f_user0_clk.!altr,socfpga-gate-clka` emac_0_clk.!altr,socfpga-gate-clka emac_1_clk.!altr,socfpga-gate-clka usb_mp_clk.!altr,socfpga-gate-clka  K¤¼#Â#spi_m_clk.!altr,socfpga-gate-clka  K¤¼  can0_clk.!altr,socfpga-gate-clka  K¤¼Âcan1_clk.!altr,socfpga-gate-clka  K¤ ¼Âgpio_db_clk.!altr,socfpga-gate-clka  K¨h2f_user1_clk.!altr,socfpga-gate-clka sdmmc_clk.!altr,socfpga-gate-clk  a j‡¼Ânand_x_clk.!altr,socfpga-gate-clk  a  nand_clk.!altr,socfpga-gate-clk  a  Sqspi_clk.!altr,socfpga-gate-clk  a  ethernet@ff7000000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac t`ÿp  âs‡macirq— stmmaceth£  ªstmmaceth¶Ñ€ 'disabledethernet@ff7020000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac t`ÿp  âx‡macirq— stmmaceth£! ªstmmaceth¶Ñ€'okayírgmiiö*7 (CPÐi2c@ffc04000!snps,designware-i2cÿÀ@ âž'okayeeprom@51 !atmel,24c32Q\ rtc@68!dallas,ds1339hi2c@ffc05000!snps,designware-i2cÿÀP ⟠'disabledi2c@ffc06000!snps,designware-i2cÿÀ` â  'disabledi2c@ffc07000!snps,designware-i2cÿÀp â¡ 'disabledgpio@ff708000!snps,dw-apb-gpioÿp€ 'disabledgpio-controller@0!snps,dw-apb-gpio-porteu§– â¤gpio@ff709000!snps,dw-apb-gpioÿp 'disabledgpio-controller@0!snps,dw-apb-gpio-porteu§– â¥gpio@ff70a000!snps,dw-apb-gpioÿp  'disabledgpio-controller@0!snps,dw-apb-gpio-porteu§– â¦sdr@ffc25000!sysconÿÂP¼Âsdramedac!altr,sdram-edac â'l2-cache@fffef000!arm,pl310-cacheÿþð â&Ÿ­ ¹ ɼÂdwmmc0@ff704000!altr,socfpga-dw-mshcÿp@ â‹Úbiuciuåïù&2sram@ffff0000 !mmio-sramÿÿspi@fff00000!snps,dw-apb-ssiÿð âš?  'disabledspi@fff01000!snps,dw-apb-ssiÿð â›?  'disabledtimer@fffec600!arm,cortex-a9-twd-timerÿþÆ â !timer0@ffc08000!snps,dw-apb-timer â§ÿÀ€timertimer1@ffc09000!snps,dw-apb-timer â¨ÿÀtimertimer2@ffd00000!snps,dw-apb-timer â©ÿÐtimertimer3@ffd01000!snps,dw-apb-timer âªÿÐtimerserial0@ffc02000!snps,dw-apb-uartÿÀ  â¢FP]""btxrxserial1@ffc03000!snps,dw-apb-uartÿÀ0 â£FP]""btxrxrstmgr@ffd05000l !altr,rst-mgrÿÐP¼Âusbphy@0y!usb-nop-xceiv'okay¼$Â$usb@ffb00000 !snps,dwc2ÿ°ÿÿ â}#otg„$ ‰usb2-phy 'disabledusb@ffb40000 !snps,dwc2ÿ´ÿÿ â€#otg„$ ‰usb2-phy'okaywatchdog@ffd02000 !snps,dw-wdtÿÐ  â« 'disabledwatchdog@ffd03000 !snps,dw-wdtÿÐ0 ⬠'disabledsysmgr@ffd08000!altr,sys-mgrsysconÿЀ@“ÿЀļÂ3-3-v-regulator!regulator-fixed£3.3V²2Z Ê2Z ¼Â #address-cells#size-cellsmodelcompatiblebootargsethernet0ethernet1serial0serial1timer0timer1timer2timer3device_typeregnext-level-cache#interrupt-cellsinterrupt-controllerlinux,phandleinterrupt-parentrangesinterrupts#dma-cells#dma-channels#dma-requestsclocksclock-namesstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phasealtr,sysmgr-sysconinterrupt-namesmac-addressresetsreset-namessnps,multicast-filter-binssnps,perfect-filter-entriesphy-moderxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxen-skew-pstxc-skew-psrxdv-skew-psrxc-skew-pspagesizegpio-controller#gpio-cellssnps,nr-gpiosaltr,sdr-sysconcache-unifiedcache-levelarm,tag-latencyarm,data-latencyfifo-depthnum-slotsbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeedvmmc-supplyvqmmc-supplynum-csreg-shiftreg-io-widthdmasdma-names#reset-cells#phy-cellsphysphy-namescpu1-start-addrregulator-nameregulator-min-microvoltregulator-max-microvolt