>8L(Altera SOCFPGA Arria 10"!altr,socfpga-arria10altr,socfpgachosen,console=ttyS0,115200 rootwaitaliases5/soc/ethernet@ff800000?/soc/ethernet@ff802000I/soc/ethernet@ff804000S/soc/serial0@ffc02000[/soc/serial1@ffc02100c/soc/timer0@ffc02700j/soc/timer1@ffc02800q/soc/timer2@ffd00000x/soc/timer3@ffd00100memorymemory@cpuscpu@0!arm,cortex-a9cpucpu@1!arm,cortex-a9cpuintc@ffffd000!arm,cortex-a9-gicsoc !simple-bussocamba !arm,amba-buspdma@ffda1000!arm,pl330arm,primecell`STUVWXYZ clkmgr@ffd04000 !altr,clk-mgr@clocksosc1 !fixed-clock+}x@main_pll!altr,socfpga-pll-clock;periph_pll!altr,socfpga-pll-clock;ethernet@ff8000000!altr,socfpga-stmmacsnps,dwmac-3.72asnps,dwmac  \BmacirqR ^disabledethernet@ff8020000!altr,socfpga-stmmacsnps,dwmac-3.72asnps,dwmac  ]BmacirqR ^disabledethernet@ff8040000!altr,socfpga-stmmacsnps,dwmac-3.72asnps,dwmac@  ^BmacirqR ^disabledgpio@ffc02900!snps,dw-apb-gpio) ^disabledgpio-controller@0!snps,dw-apb-gpio-porteu pgpio@ffc02a00!snps,dw-apb-gpio* ^disabledgpio-controller@0!snps,dw-apb-gpio-porteu qgpio@ffc02b00!snps,dw-apb-gpio+ ^disabledgpio-controller@0!snps,dw-apb-gpio-porteu ri2c@ffc02200!snps,designware-i2c" i ^disabledi2c@ffc02300!snps,designware-i2c# j ^disabledi2c@ffc02400!snps,designware-i2c$ k ^disabledi2c@ffc02500!snps,designware-i2c% l ^disabledi2c@ffc02600!snps,designware-i2c& m ^disabledl2-cache@fffff000!arm,pl310-cache dwmmc0@ff808000!altr,socfpga-dw-mshc bsram@ffe00000 !mmio-sramrstmgr@ffd05000 !altr,rst-mgrPsysmgr@ffd06000!altr,sys-mgrsyscon`timer@ffffc600!arm,cortex-a9-twd-timer  timer0@ffc02700!snps,dw-apb-timer s'timer1@ffc02800!snps,dw-apb-timer t(timer2@ffd00000!snps,dw-apb-timer utimer3@ffd00100!snps,dw-apb-timer vserial0@ffc02000!snps,dw-apb-uart  n^okayserial1@ffc02100!snps,dw-apb-uart! ousbphy@0!usb-nop-xceiv^okayusb@ffb00000 !snps,dwc2 _ usb2-phy ^disabledusb@ffb40000 !snps,dwc2 ` usb2-phy ^disabledwatchdog@ffd00200 !snps,dw-wdt w ^disabledwatchdog@ffd00300 !snps,dw-wdt x ^disabled #address-cells#size-cellsmodelcompatiblebootargsethernet0ethernet1ethernet2serial0serial1timer0timer1timer2timer3device_typeregnext-level-cache#interrupt-cellsinterrupt-controllerlinux,phandleinterrupt-parentrangesinterrupts#dma-cells#dma-channels#dma-requests#clock-cellsclock-frequencyclocksinterrupt-namesmac-addressstatusgpio-controller#gpio-cellssnps,nr-gpioscache-unifiedcache-levelfifo-depth#reset-cellsreg-shiftreg-io-width#phy-cellsphysphy-names